This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
In some conventional circuit designs, write assist schemes may be designed to assist with various write operations that seek to improve write margin by decreasing the write time. However, conventional negative bitline write assist is ineffective and deficient in that conventional operation often results in write failure. For instance, if a bitline is kept to a Vss level through a write driver for a long duration of time, then the bitcell may flip polarity, but the time taken to flip the bitcell may be large, e.g., when the bitcell does not suffer from a DC writeability problem. Further, in conventional negative bitline write assist, instead of keeping the bitline to a Vss level, the bitline may float and inject negative charge through capacitive coupling. For instance, as the bitline goes negative, the bitcell may flip polarity. However, because the bitline is floating and negative, the bitline may start to go high due to leakage from other access transistors of unselected bitcells in the column, from some column multiplexer transistors, and/or from the write driver. Therefore, if the applied negative voltage is not sufficient to flip the bitcell, then giving more write time may not provide write assist when the bitline is charging-up.